1. Field of the Invention
The present invention relates to a level shifter, and more particularly to a level shifter of a semiconductor memory device that can reduce leakage current and avoid operation delay of the device and that can implement a small-sized, lightweight and highly integrated device.
2. Description of the Related Art
A semiconductor memory device is a device capable of implementing Complementary Metal Oxide Semiconductor (CMOS) transistors and passive devices on a silicon wafer and writing and reading data. Most of the semiconductor devices are mounted on a board serving as an important element configuring a system. A semiconductor device externally receives an appropriate drive voltage (typically indicated by Vcc or Vdd). In some cases, a semiconductor device must internally generate a voltage less or higher than Vdd.
In this case, circuits using power supply voltages with different voltage levels must be coupled to a device for converting a voltage level. Otherwise, there is a problem in that a corresponding circuit or device may erroneously operate. For example, the semiconductor device of a Dynamic Random Access Memory (DRAM) configures a logic device using a CMOS transistor having an inverter function. In this case, where a voltage at a source terminal of a P-channel Metal Oxide Semiconductor (PMOS) transistor (hereinafter, referred to as “PMOS”) is a threshold voltage higher than that at its gate terminal, that is, Vgs<Vth (wherein Vgs denotes a voltage difference between gate and source terminals of the PMOS and Vth denotes the threshold voltage of the PMOS), the PMOS must be turned off. However, there is a problem in that the PMOS may not be fully turned off because of physical characteristics of the PMOS. If the voltage at the source terminal of the PMOS is higher than that at the gate terminal of the PMOS and a voltage difference is less than the threshold voltage, there is another problem in that leakage current is incurred and hence circuit characteristics are degraded. In order to solve the problem, a special voltage level-shifting device, i.e., a level shifter, is used when a circuit based on a different drive voltage level is provided.
FIG. 1A is a circuit diagram illustrating a conventional level shifter. FIG. 1A shows the level shifter that receives a voltage V1 of a first voltage level and outputs a voltage V2 of a second voltage level. An input signal inputted into the level shifter is a signal having both V1 and Vss levels.
A circuit operation will be described with reference to FIG. 1A. Here, a node A is coupled between a PMOS P1 provided in a pull-up driver 100 and an N-channel Metal Oxide Semiconductor (NMOS) transistor (hereinafter, referred to as “NMOS”) N1 provided in a pull-down driver 200, and a node B is coupled between a PMOS P2 provided in the pull-up driver 100 and an NMOS N2 provided in the pull-down driver 200.
First, when an input signal inputted into the level shifter is a Vss level signal, an inverter I10 inverts the input signal and a voltage at a node C has a V1 level, such that the NMOS N1 is turned on and a voltage at the node A is in a Vss level state by a pull-down operation. Subsequently, the PMOS P2 is turned on in response to a Vss level signal at the node A, and a voltage at the node B is in a V2 level state by a pull-up operation. Thus, when the input signal is the Vss level signal, the voltage of an output signal of the level shifter has the Vss level after a signal from the node B is inverted by an inverter I30. Here, the NMOS N2 receives the Vss level signal from a node D through its gate and is in an OFF state, after an inverter I20 inverts the signal from the node C. The PMOS P1 receives the V2 level signal from the node B and is in the OFF state.
At this point, when the input signal is shifted from the Vss level signal to the V1 level signal, the inverter I10 inverts the input signal, such that a voltage level at the node C is shifted from the V1 level to the Vss level. The NMOS N1 receiving the Vss level signal through its gate is turned off. After the inverter I20 inverts the signal from the node C, a voltage level at the node D is shifted from the Vss level to the V1 level. As the NMOS N2 receives the V1 level signal from the node D through its gate and is switched from the OFF state to the ON state, a voltage level at the node B is shifted from the V2 level to the Vss level by the pull-down operation. After the signal from the node B is inverted by the inverter I30, a voltage level of the output signal is shifted from the Vss level to the V2 level.
At this point, as the voltage level at the node B is shifted from the V2 level to the Vss level, the PMOS P1 receives the Vss level signal through its gate and is switched from the OFF state to the ON state, such that the voltage level at the node A is pulled up to the V2 level by the pull-up operation. The PMOS P2 receives the voltage of the V2 level from the node A through its gate and is switched from the ON state to the OFF state. Consequently, when the input signal level is shifted from the Vss level to the V1 level, the output signal level is shifted from the Vss level to the V2 level.
Subsequently, when the input signal level is again shifted from the V1 level to the Vss level, the voltage level at the node C is shifted from the Vss level to the V1 level and the NMOS N1 is turned on. Thus, the voltage at the node A is shifted from the V2 level to the Vss level by the pull-down operation. Because the PMOS P2 receives the voltage of the Vss level from the node A and is switched from the OFF state to the ON state, the voltage level at the node B is shifted from the Vss level to the V2 level by the pull-up operation. Thus, after the signal from the node B is inverted by the inverter I30, the output signal level is shifted from the V2 level to the Vss level.
At this point, as the voltage level at the node D is shifted from the V1 level to the Vss level, the NMOS N2 is switched from the ON state to the OFF state. The PMOS P1 receives the voltage of the V2 level from the node A through its gate and is switched from the ON state to the OFF state. Consequently, when the input signal level is shifted from the V1 level to the Vss level, the output signal level is shifted from the V2 level to the Vss level.
The level shifter plays a role for receiving a signal of a predetermined voltage level and outputting a signal of a different voltage level by repeating a series of operations described above. However, while the circuit operates in the conventional level shifter, the PMOS P1 and NMOS N1 or the PMOS P2 and NMOS N2 can be simultaneously turned on at the moment when the input signal level is shifted. Thus, as an electric current channel is incurred between a V2 power supply and ground, there are problems in that leakage current is incurred and a voltage level-shifting operation for the output signal is delayed.
That is, when the input signal level is shifted from the Vss level to the V1 level, the voltage level at the node D is shifted from the Vss level to the V1 level. The NMOS N2 receives a signal of the V1 level from the node D and is switched from the OFF state to the ON state. Thus, the voltage level at the node B is shifted from the V2 level to the Vss level by the pull-down operation. At this point, the PMOS P2 must be fully turned off. However, as the PMOS P2 and the NMOS N2 are simultaneously turned on because the PMOS P2 is not fully turned off and maintains the ON state for a predetermined time, an electric current channel is formed and hence leakage current may flow from the V2 power supply to the ground. This leakage current causes operation delay when the voltage level at the node B is shifted from the V2 level to the Vss level. Consequently, there is another problem in that the operation delay is incurred when the voltage level is shifted from the Vss level to the V2 level.
Similarly, when the input signal level is shifted from the V1 level to the Vss level, the PMOS P1 must be fully turned off. However, as the PMOS P1 and the NMOS N1 are simultaneously turned on because the PMOS P1 is not fully turned off and maintains the ON state for a predetermined time, an electric current channel is formed and hence leakage current may flow from the V2 power supply to the ground. This leakage current causes operation delay when the voltage level at the node A is shifted from the V2 level to the Vss level. Consequently, there is another problem in that the operation delay is incurred when the voltage level is shifted from the V2 level to the Vss level.
FIG. 1B shows waveforms of an input signal, an output signal and node signals. It can be seen that the above-described operation delay in the conventional level shifter is incurred.
Of course, there may be taken into account a method for improving operation performance of the level shifter by means of a method for sufficiently improving electric current drive capabilities of the NMOS N1 and the NMOS N2 to increase switching rates of the PMOS P1 and the PMOS P2. However, because this method inherently increases device size to improve the electric current drive capabilities of the NMOS N1 and the NMOS N2, a layout area of the semiconductor device is increased and a highly integrated semiconductor device cannot be implemented. When a voltage difference between the input and output signals is increased, there is a problem in that the size of the NMOS must be increased. Moreover, there is another problem in that operation delay may be caused by an inappropriate operating state caused by an undesired electric current channel in the PMOS P1 and NMOS N1 or the PMOS P2 and NMOS N2.